1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device having a trench-type isolation region, and a method of fabricating the same. The present invention particularly relates to the structure of a trench-type isolation region of a nonvolatile semiconductor memory device in which a floating gate has a two-layered gate structure which is formed in self-alignment with the isolation region and an active region, and a method of forming the structure.
2. Description of the Related Art
A flash memory is well known as a nonvolatile semiconductor memory device in which data is electrically rewritten, and which is suited to increasing the density and capacity. In the flash memory, a plurality of cell transistors are arranged in the form of an array. Each cell transistor is a MOS transistor having a two-layered gate structure in which a floating gate and control gate are stacked. In a NAND flash memory, a plurality of cell transistors are connected in series.
FIG. 1 shows the sectional structure of a memory cell of a conventional NAND flash memory. Reference numeral 301 denotes a semiconductor substrate; 302, a first gate insulating film formed on the semiconductor substrate; 303 and 304, first and second polysilicon films, respectively, forming a floating gate of the memory cell; 306, a silicon oxide film; 307; an isolation region made of an insulating film; 309; a second gate insulating film; and 310, a third polysilicon film which functions as a control gate of the memory cell and a local source line.
In this flash memory shown in FIG. 1, in the direction in which the control gate runs, a coupling capacitance is present between the floating gates of two memory cells adjacent to each other via the isolation region 307. This capacitive coupling between adjacent cells may cause adverse effects.
Jpn. Pat. Appln. KOKAI Publication No. 2002-57230 has proposed a structure in which an isolation insulating film and a gate insulating film on the surface of a substrate are etched after floating gates are formed by etching, thereby decreasing the step of the isolation insulating film.
Also, Jpn. Pat. Appln. KOKAI Publication No. 2003-78047 describes a structure in which an isolation region is formed in self-alignment with an electrode layer made of one conductor layer, in order to decrease the size of a memory cell.
In the conventional NAND flash memories as described above, the coupling capacitance present between the floating gates of two memory cells adjacent to each other via the isolation region in the direction in which the control gate runs causes adverse effects between these cells.